This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device such as a DRAM with high integration density and a method for manufacturing the same.
With an increase in the integration density of a recent semiconductor integrated circuit, particularly a semiconductor memory device such as a DRAM (dynamic random access memory), the area of a memory cell tends to be reduced. Therefore, it becomes necessary to effect the fine patterning process and this increases the load on the lithography technology, and in the normal exposure technique, it becomes difficult to meet the requirement for the minimum processing size (which is hereinafter referred to as F) or the accuracy of alignment between patternings.
In order to alleviate the load for the lithography technology, the cell Layout having the same memory cell area and capable of alleviating the requirement for the minimum processing size is proposed. For example, in a DRAM memory cell constructed by one transistor and one capacitor, an area of 8.times.F.sup.2 is required in the prior art if the minimum processing size (gate length) is set to F, but in the above memory cell, only an area of 4.times.F.sup.2 to 6.times.F.sup.2 is required. That is, since the memory cells of the same cell area can be processed with the larger minimum processing size, the load on the lithography technology can be reduced.
FIGS. 1A and 1B show a memory cell having an area of 6.times.F.sup.2 previously invented by the inventor of this application. FIG. 1A is a plan view of the memory cell and FIG. 1B is a cross sectional view taken along the line 1B-1B of FIG. 1A.
The memory cell is constructed by a cell transistor and a cell capacitor. The cell transistor has source and drain diffusion layers 71a, 71b formed on a semiconductor substrate 2 and a gate electrode 17 formed over the semiconductor substrate 2 with a gate insulating film 16 disposed therebetween and the gate electrode 17 constructs a word line. The cell capacitor is constructed by the semiconductor substrate 2 and a storage electrode 9 filled in an opening (trench) 7 formed in the semiconductor substrate 2 while a capacitor insulating film 8 is formed on the wall surface of the opening 7 and disposed between the wall surface and the storage electrode. The source or drain diffusion layer 71a of the transistor is connected to the storage electrode 9 of the capacitor via a connection electrode 73 and the other diffusion layer 71b of the transistor is connected to a bit line 24 via a bit line connection hole 23.
With the memory cell shown here, even when the gate electrode 17 is first formed and then the diffusion layers 71a, 71b are formed in self-alignment with the gate electrode 17, a certain area of the diffusion layer 71a can be stably obtained by setting the opening 7 in position shifted in a direction along the word line with respect to an element formation region 72, and therefore, it becomes possible to set the opening 7 and the gate electrode 17 close to each other, thus making it possible to attain the area of 6.times.F.sup.2.
However, with the above structure, the diffusion layer 71a is formed to have a width which is half the width of the element formation region 72 in the word line direction and thus the width becomes substantially half the minimum processing size. Therefore, in order to obtain a certain area of the diffusion layer 71a, it is required to accurately control the processing dimensional precision and the accuracy of alignment between the patternings for the opening 7 and the element formation region 72. For example, if the area of the diffusion region 71a varies or the area therefor cannot be obtained, the contact resistance between the storage electrode 9 and the diffusion layer 71a increases or varies, thereby making it difficult to attain a stable operation of the memory cell.
The above problem occurs not only in the memory cell having the area of 6.times.F.sup.2 but also in a memory cell of other configuration such as a memory cell having an area of 8.times.F.sup.2.
Thus, in a conventional semiconductor memory device having an area of 6.times.F.sup.2 or the like and a method for manufacturing the same, if the processing dimensional precision and the accuracy of alignment, between the patternings for the opening in which the storage electrode is to be filled and the element formation region in which the transistor is formed, are not sufficiently high, it becomes difficult to obtain a sufficiently large area for the diffusion region of the transistor and the connection resistance between the transistor and the storage electrode increases, thereby preventing the stable operation of the semiconductor memory device.